This application is related to and claims priority from Korean Application No. 2001-26998, filed May 17, 2001, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and methods of operating the same and, more particularly, to control circuits for integrated circuit devices and methods of controlling the same.
In conventional integrated circuit devices, in order to determine whether the device is normal, i.e. not defective, parameters such as voltage and time are measured at a package level. If the measured parameters satisfy a predetermined value of the integrated circuit device, for example, an integrated circuit memory device, the integrated circuit memory device may be regarded as normal. On the other hand, if the measured parameters do not satisfy the predetermined value, the integrated circuit memory device may be regarded as defective.
Parameters that are typically measured may include, for example, internal power voltage, high voltage, substrate voltage, a time period tSAC (time from generation of a clock signal to time of valid data output) and output data hold time tOH. If these parameters do not meet the predetermined specifications at a package level, the integrated circuit device may be regarded as defective and be discarded. Accordingly, each time an integrated circuit device is discarded due to a nonconforming parameter, the manufacturing yield of integrated circuit memory devices may be lowered.
Embodiments of the present invention provide integrated circuit devices including a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective.
In some embodiments of the present invention the predetermined circuit voltage specification is a reference voltage and the voltage control circuit increases and/or decreases the circuit voltage based on a relationship between the circuit voltage and the reference voltage.
In some embodiments of the present invention, the voltage control circuit may increase the circuit voltage if the circuit voltage is less than the reference voltage and/or may decrease the circuit voltage if the circuit voltage is greater than the reference voltage.
In further embodiments of the present invention, the circuit voltage may include at least one of an internal power voltage, a bit line pre-charge voltage, a high voltage and a substrate voltage.
In still further embodiments of the present invention, the voltage control circuit may be an internal power voltage generating circuit and the circuit voltage may be an internal power voltage. The internal power generating circuit may include a mode setting unit that receives a plurality of input signals and sets at least one input control signal responsive to the plurality of input signals. The internal power generating circuit may further include a voltage level control unit that sets the state of at least one output control signal responsive to the at least one input control signal and turns a switching circuit on and/or off in response to the at least one output control signal. Finally, the internal power generating circuit may include an internal power voltage generating unit that compares the internal power voltage received from the switching circuit to the reference voltage and increases and/or decreases the internal power voltage responsive to the relationship between the internal power voltage and the reference voltage.
In some embodiments of the present invention, the voltage level control unit may include a control signal generating circuit and a switching circuit. The control signal generating circuit may set the state of the at least one output control signal responsive to the at least one input control signal.
In further embodiments of the present invention the voltage control circuit may include a bit line pre-charge voltage generating circuit and the circuit voltage may include a bit line pre-charge voltage. The bit line pre-charge voltage generating circuit may include a mode setting unit, a first voltage level control unit, a second voltage level control unit, and a bit line pre-charge voltage generating unit. The mode selecting unit may receive a plurality of input signals and set at least one first input control signal and at least one second input control signal responsive to the plurality of input signals. The first voltage level control unit may set the state of at least one first output control signal responsive to the at least one first input control signal and turn a first switching circuit on and/or off in response to the at least one first output control signal. The second voltage level control unit may set the state of at least one second output control signal responsive to the at least one second input control signal and turn a second switching circuit on and/or off in response to the at least one second output control signal. Finally, the bit line pre-charge voltage generating unit may compare the bit line pre-charge voltage to the reference voltage and increases and/or decreases the bit line pre-charge voltage responsive to the relationship between the bit line pre-charge voltage and the reference voltage.
In still further embodiments of the present invention voltage control circuit may include a substrate voltage level detecting circuit and the circuit voltage may include a substrate voltage. The substrate voltage level detecting circuit may include a mode setting unit, a first voltage level control unit, a second voltage level control unit, and a substrate voltage detecting unit. The mode setting unit may receive a plurality of input signals and may set at least one first input control signal and at least one second input control signal responsive to the plurality of input signals. The first voltage level control unit may set the state of at least one first output control signal responsive to the at least one first input control signal and may turn a first switching circuit on and/or off in response to the at least one first output control signal. The second voltage level control unit may set the state of at least one second output control signal responsive to the at least one second input control signal and may turn a second switching circuit on and/or off in response to the at least one second output control signal. Finally, the substrate voltage detecting unit may compare the substrate voltage to the reference voltage and increase and/or decrease the substrate voltage responsive to the relationship between the substrate voltage and the reference voltage.
In some embodiments of the present invention, the voltage control circuit may include a high voltage level detecting circuit and the circuit voltage may include a high voltage. The high voltage level detecting circuit may include a mode setting unit, a first voltage level control unit, a second voltage level control unit, and a high voltage detecting unit. The mode setting unit may receive a plurality of input signals and may set at least one first input control signal and at least one second input control signal responsive to the plurality of input signals. The first voltage level control unit may set the state of at least one first output control signal responsive to the at least one first input control signal and may turn a first switching circuit on and/or off in response to the at least one first output control signal. The second voltage level control unit may set the state of at least one second output control signal responsive to the at least one second input control signal and turns a second switching circuit on and/or off in response to the at least one second output control signal. Finally, a high voltage level detecting unit may compare the high voltage to the reference voltage and increase and/or decrease the high voltage responsive to the relationship between the high voltage and the reference voltage.
In further embodiments of the present invention a signal delay time control circuit is provided. The signal time delay control circuit may be configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective.
In still further embodiments of the present invention the predetermined circuit delay time is a reference delay time and the signal delay time control circuit increases and/or decreases the circuit delay time responsive to the relationship between the circuit delay time and the reference delay time.
In still further embodiments of the present invention, methods of operating a voltage and/or time control circuit are provided according to embodiments of the present invention.